This invention relates, in general, to semiconductor memories, and more particularly, to reconfigurable SRAMs (Static Random Access Memories) for providing a variety of different word widths.
Gate arrays are well known in the semiconductor arts for building semi-custom integrated circuits. A gate array is a semiconductor die fabricated with a large array of transistors and I/O (Input/Output) circuitry. A gate array is pre-processed up to a transistor level but does not include the interconnection of the transistor array and I/O circuitry. The only processing required to form a circuit on a gate array is metallization or interconnection of the transistor array to a user specific design. In general, two or three layers of metal are used for interconnection on a gate array.
Gate arrays are designed to be extremely efficient at forming simple logic blocks commonly used in digital circuits. For example, NAND gates, NOR gates, inverters, and flip flops. Efficiency of metallization (or routing) of a gate array is measured by the total number of transistors used versus the total number of transistors in the gate array. Circuits formed with the simple logic blocks described above typically achieve efficiencies of approximately 80 percent or less.
A problem common to a gate array is that they are inefficient in forming large complex circuit blocks. For example, a SRAM (static random access memory) is a circuit typically used in the design of a digital circuit that is classified as a large circuit block. Gate array manufacturers have minimally satisfied customer demands for SRAMs on gate arrays by providing :software to build an SRAM on a transistor array of a gate array. Memory intensive circuit designs use up a majority of a transistor array building a SRAM leaving only a small portion of the transistor array for building other circuitry. Moreover, a general trend for gate array users is to use larger memory sizes or multiple memories with different word widths. This is further complicated by an increasing need for more transistors to form other circuitry other than memories.
A SRAM formed in a transistor array of a SRAM is transistor intensive, each memory cell requires 6 transistors. Transistors of a gate array are not optimized for providing a memory cell having small dimensions. In fact, just the opposite is true, a transistor grouping on a transistor array is arranged for providing routing channels to simplify metallization. Furthermore, gate array memories fall short on performance and density when compared to commercially available memories. It is well known that SRAMs designed for the commercial market have memory cells that are optimized for memory cell size to increase both density and performance. Full custom SRAMs are known as "full diffused" SRAMs as all circuit elements are customized to maximize performance and decrease size. This approach works well since a semiconductor manufacturer sells millions of memories of a single type. On a gate array the opposite is true, each user may require a different memory size and a different memory word width. Flexibility is an important parameter for any memory provided on a gate array.
It would be of great benefit if a SRAM could be provided that is easily implemented on a gate array, has increased density and has performance approaching that of a full diffused memory, and is configurable for different word widths.